MT40A1G16KD-062E:E

MT40A1G16KD-062E:E DDR4 SDRAM is a high-speed dynamic random-access memory internally configured as an eight-bank DRAM for the x16 configuration and as a 16-bank DRAM for the x4 and x8 configurations. The DDR4 SDRAM uses an 8n-prefetch architecture to achieve high-speed operation. The 8n-prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins. A single READ or WRITE operation for the DDR4 SDRAM consists of a single 8n-bit wide, four-clock data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.

• On-die, internal, adjustable VREFDQ generation, 1.2V pseudo open-drain I/O
• 8n-bit prefetch architecture, programmable data strobe preambles
• Data strobe preamble training, command/address latency (CAL)
• Multipurpose register READ and WRITE capability
• Write leveling, self refresh mode, low-power auto self refresh (LPASR)
• Temperature controlled refresh, fine granularity refresh, self refresh abort, maximum power saving
• Nominal, park, and dynamic on-die termination (ODT), data bus inversion (DBI) for data bus
• Per-DRAM addressability, connectivity test, JEDEC JESD-79-4 compliant, sPPR and hPPR capability
• 1 Gig x 16 configuration, 0 to +95°C commercial operating case temperature
• 96-ball FBGA package, tCK = 0.625ns, CL = 22