MT41J128M16JT-093:K

MT41J128M16JT-093:K is a DDR3 SDRAM. It uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR3 SDRAM effectively consists of a single 8n-bit-wide, four-clock cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. The differential data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the DDR3 SDRAM input receiver. DQS is center-aligned with data for WRITEs. The read data is transmitted by the DDR3 SDRAM and edge-aligned to the data strobes. Read and write accesses to the DDR3 SDRAM are burst-oriented. Accesses start at a selected location and continue for a programmed number of locations in a programmed sequence.

• 128M16 configuration, tCK = 0.938ns, CL = 14 cycle time
• Differential bidirectional data strobe, 8n-bit prefetch architecture
• Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals
• Programmable CAS READ latency (CL), posted CAS additive latency (AL)
• Programmable CAS WRITE latency (CWL) based on tCK
• Self refresh temperature (SRT), automatic self refresh (ASR), write levelling
• Fixed burst length (BL) of 8 and burst chop (BC) of 4 (via the mode register set [MRS])
• Industrial temperature range from -40°C to +95°C
• Package style is 96-ball FBGA