MT41K128M16JT-125 AUT:K

MT41K128M16JT-125 AUT:K is a DDR3L SDRAM. It uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single READ or WRITE operation for the DDR3 SDRAM consists of a single 8n-bit-wide, four-clock-cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one half-clock-cycle data transfers at the I/O pins.

• 128Meg x 16 configuration, data rate is 1600MT/s, automotive certification
• Packaging style is 96-ball FBGA
• Timing (cycle time) is 1.25ns at CL = 11 (DDR3-1600)
• Ultra-high temperature range is –40°C to +125°C
• Operating supply voltage is 1.283V to 1.45V
• Differential bidirectional data strobe, 8n-bit prefetch architecture
• Programmable CAS (READ) latency (CL), programmable posted CAS additive latency (AL)
• Programmable CAS (WRITE) latency (CWL), self refresh mode
• Self refresh temperature (SRT), automatic self refresh (ASR)
• Write levelling, multipurpose register, output driver calibration