MT41K128M8DA-107 IT:J

MT41K128M8DA-107 IT:J is a 1.35V DDR3L SDRAM device. The double data rate architecture is an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR3 SDRAM effectively consists of a single 8n-bit-wide, four-clock-cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. The differential data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the DDR3 SDRAM input receiver. DQS is center-aligned with data for WRITEs. The read data is transmitted by the DDR3 SDRAM and edge-aligned to the data strobes. The DDR3 SDRAM operates from a differential clock (CK and CK#). The crossing of CK going HIGH and CK# going LOW is referred to as the positive edge of CK. Control, command, and address signals are registered at every positive edge of CK.

• 128 Meg x 8 configuration, tCK = 1.07ns, CL = 13 speed grade, 8K refresh count
• 16K A[13:0] row address, 8 BA[2:0] bank address, 2K A[11, 9:0] column address, 1KB page size
• 1866MT/s data rate, 13-13-13 target tRCD-tRP-CL, 13.91ns tRCD, 13.91ns tRP, 13.91ns CL
• VDD = VDDQ = +1.35V (1.283V to 1.45V), backward compatible to VDD = VDDQ = 1.5V ±0.075V
• Differential bidirectional data strobe, 8n-bit prefetch architecture differential clock inputs
• 8 internal banks, nominal and dynamic on-die termination for data, strobe, and mask signals
• Programmable CAS (READ) latency, programmable CAS additive latency (AL), automatic self refresh
• Programmable CAS (WRITE) latency (CWL), self refresh mode, self refresh temperature
• Fixed burst length (BL) of 8 and burst chop (BC) of 4 (via the mode register set [MRS])
• 78-ball FBGA package, commercial operating temperature range from 0°C to +95°C