MT48LC4M32B2B5-6A AAT:L

MT48LC4M32B2B5-6A AAT:L is an automotive SDR SDRAM. The 128Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 134,217,728 bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x4’s 33,554,432-bit banks are organized as 4096 rows by 2048 columns by 4bits. Each of the x8’s 33,554,432-bit banks are organized as 4096 rows by 1024 columns by 8bits. Each of the x16’s 33,554,432-bit banks are organized as 4096 rows by 512 columns by 16bits. The 128Mb SDRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a highspeed, fully random access.

• PC100-compliant, fully synchronous; all signals registered on the positive edge of the system clock
• Internal pipelined operation; column address can be changed every clock cycle
• Internal banks for hiding row access/precharge
• Auto precharge, includes concurrent auto precharge and auto refresh modes
• LVTTL-compatible inputs and outputs
• Single 3.3V ±0.3V power supply, 8D response time
• Supports CAS latency (CL) of 1, 2, and 3
• AEC-Q100 qualified, PPAP submission
• 4 Meg x 32 architecture, 6ns (167MHz) timing (cycle time)
• 90-ball VFBGA (8mm x 13mm) package, -40°C to +105°C automotive operating temperature range