MTA18ASF4G72PZ-3G2F1

MTA18ASF4G72PZ-3G2F1 is a high-speed DDR4 SDRAM module. DDR4 SDRAM module benefits from DDR4 SDRAM's use of an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single READ or WRITE operation for the DDR4 SDRAM effectively consists of a single 8n-bitwide, four-clock data transfer at the internal DRAM core and eight corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins. DDR4 module uses two sets of differential signals: DQS_t and DQS_c to capture data and CK_t and CK_c to capture commands, addresses, and control signals. Differential clocks and data strobes ensure exceptional noise immunity for these signals and provide precise crossing points to capture input signals.

• Supports ECC error detection and correction
• Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals
• Low-power auto self refresh (LPASR), on-die VREFDQ generation and calibration
• Single-rank, on-board I2C temperature sensor with integrated serial presence-detect (SPD) EEPROM
• Fixed burst chop (BC) of 4 and burst length (BL) of 8 via the mode register set (MRS)
• Selectable BC4 or BL8 on-the-fly (OTF), gold edge contacts
• Fly-by topology, terminated control, command, and address bus
• 32GB module density, 4 Gig x 72 configuration
• 25.6GB/s module bandwidth, 0.62ns/3200MT/s memory clock/data rate
• 288-pin DIMM package, commercial operating temperature range from 0°C ≤ TOPER ≤ 95°C