74HC595D-Q100,118

74HC595D-Q100,118 is an 8bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. This device features a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset active-low MR input. A LOW on active-low MR will reset the shift register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in the shift register is transferred to the storage register on a LOW-to-HIGH transition of the STCP input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. Data in the storage register appears at the output whenever the output enable input (active-low OE) is LOW. A HIGH on active-low OE causes the outputs to assume a high-impedance OFF-state. It is used in applications such as serial-to-parallel data conversion, remote control holding register.

• 8bit serial input, 8bit serial or parallel output
• Storage register with 3-state outputs, shift register with direct clear
• 100MHz (typical) shift out frequency, complies with JEDEC standard no. 7A
• CMOS input level, ESD protection, supply voltage range from 2V to 6V
• Automotive product qualification in accordance with AEC-Q100 (Grade 1)
• Input leakage current is ±1.0μA maximum at (VI = VCC or GND; VCC = 6V, -40°C to +85°C)
• Supply current is 80μA maximum at (VI = VCC or GND; IO = 0A; VCC = 5.5V, -40°C to +85°C)
• Input capacitance is 3.5pF typical at (-40°C to +85°C)
• Propagation delay is 52ns typical at (VCC = 2V, 25°C)
• Operating temperature range from -40°C to +125°C, SO16 package