AD9511BCPZ

AD9511 1.2GHz clock distribution IC. It provides a multi-output clock distribution IC function along with an on-chip PLL core. The design emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this part. The PLL section consists of a programmable reference divider a low noise phase frequency detector a precision charge pump and a programmable feedback divider. By connecting an external VCXO or VCO to the CLK2/CLK2B pins, frequencies up to 1.6GHz may be synchronized to the input reference. Each output has a programmable divider that may be bypassed or set to divide by any integer up to 32. Application includes low jitter, low phase noise clock distribution, clocking high-speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs, high performance wireless transceivers, high performance instrumentation, broadband infrastructure.

• Low phase noise phase-locked loop core, programmable dual-modulus prescaler
• Programmable charge pump (CP) current, phase select for output-to-output coarse delay adjust
• Fine delay adjust on 1 LVDS/CMOS output, serial control port
• Input frequency range from 0 to 250MHz (VS=3.3V ± 5%, VS ≤ VCPS ≤ 5.5V, TA=25°C, typ)
• Typical input sensitivity is 150mV p-p (VS=3.3V ± 5%, VS ≤ VCPS ≤ 5.5V, TA=25°C, typ)
• Maximum PFD input frequency is 100MHz (ant backlash pulse width 0Dh<lt/>1:0<gt/>=01b)
• Typical high value is 4.8mA (with CPRSET=5.1kohm, VS=3.3V ± 5%, VS ≤ VCPS ≤ 5.5V, TA=25°C, typ)
• Maximum input frequency is 1.6GHz (frequencies <gt/> 1200MHz or 800MHz require a minimum divide-by-2)
• Maximum output frequency is 1200MHz (VS=3.3V ± 5%, VS ≤ VCPS ≤ 5.5V, TA=25°C, typ)
• 48-lead LFCSP package, temperature range from -40°C to +85°C

Notes

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