MT46H64M32LFBQ-48 IT:C

MT46H64M32LFBQ-48 IT:C is a LPDDR SDRAM. It is a 2Gb mobile low-power DDR SDRAM and a high-speed CMOS, dynamic random-access memory containing 2,147,483,648 bits. It is internally configured as a quad-bank DRAM. Each of the x16’s 536,870,912-bit banks is organized as 16,384 rows by 2048 columns by 16 bits. Each of the x32’s 536,870,912-bit banks is organized as 16,384 rows by 1024 columns by 32 bits. It has a Internal, pipelined double data rate (DDR) architecture, two data accesses per clock cycle. this memory has deep power-down (DPD), status read register (SRR) and selectable output drive strength (DS).

• Operating voltage range is 1.8V, deep power-down (DPD)
• 64Meg x 32 configuration
• Packaging style is 90-ball (8mm x 13mm) VFBGA, “green”
• Timing (cycle time) is 4.8ns at CL = 3 (208 MHz), JEDEC-standard addressing
• Operating temperature range is –40˚C to +85˚C, design generation
• Clock rate is 208MHz, bidirectional data strobe per byte of data (DQS)
• Differential clock inputs (CK and CK#), commands entered on each positive CK edge
• DQS edge-aligned with data for READs; centeraligned with data for WRITEs
• Concurrent auto precharge option is supported, auto refresh and self refresh modes
• Temperature-compensated self refresh (TCSR), partial-array self refresh (PASR)