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Evaluation Kit, HMC7044LP10BE, Dual Loop Clock Jitter Cleaner, 3.3 to 5 V Supply


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Newark Part No.:
Technical Datasheet:
EK1HMC7044LP10B   Datasheet
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Product Overview

EK1HMC7044LP10B is an evaluation board to evaluate the HMC7044 dual loop clock jitter cleaner. The HMC7044 meets the requirements of multicarrier GSM and LTE base station designs and offers a wide range of clock management and distribution features to simplify baseband and radio card clock tree designs. The high performance dual-loop core of the HMC7044 enables the base station designer to attenuate the incoming jitter of a primary system reference clock, such as a CPRI source, with the help of the narrow-band configured first PLL loop, which disciplines an external VCXO and to generate the low phase noise, high frequency clocks with the wider-band second PLL to drive data converter sample clock inputs.

Product Information

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Analog Devices


Clock & Timing

Clock Jitter Cleaner

Evaluation Board HMC7044LP10BE, USB Interface Board and USB Cable


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Technical Documents (1)

Available for back order

More stock available to supplier lead times which is approximately 10/16/23

UK Stock


Delivery in 2-4 business days from our UK warehouse for in stock items

Delivery in 2-4 business days
(UK Stock)

Due to market conditions delivery times are for general guidance only and may be subject to change at short notice


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