PCA9512ADP,118

The PCA9512ADP,118 is a hot swappable I²C Bus and SMBus Buffer allows I/O card insertion into a live backplane without corruption of the data and clock buses and includes two dedicated supply voltage pins to provide level shifting between 3.3 and 5V systems while maintaining the best noise margin for each voltage level. Either pin may be powered with supply voltages ranging from 2.7 to 5.5V with no constraints on which supply voltage is higher. Control circuitry prevents the backplane from being connected to the card until a stop bit or bus idle occurs on the backplane without bus contention on the card. When the connection is made, it provides bidirectional buffering, keeping the backplane and card capacitances isolated. The rise time accelerator circuitry allows the use of weaker DC pull-up currents while still meeting rise time requirements. The PCA9512A incorporates a digital input pin that enables and disables the rise time accelerators on all four SDAn and SCLn pins.

• Bidirectional buffer for SDA and SCL lines increases fan-out and prevents SDA and SCL corruption
• Idle detect
• Rise time accelerator circuitry hardware disable pin for lightly loaded systems
• Built-in DV/Dt rise time accelerators on all SDA and SCL lines
• High-impedance SDAn and SCLn pin
• 1V Precharge on all SDAn and SCLn pins
• Supports clock stretching and multiple master arbitration and synchronization
• Latch-up testing is done to JEDEC standard JESD78 which exceeds 100mA

Applications

Signal Processing, Automation & Process Control, Wireless, Communications & Networking