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| Cantidad | Precio en USD |
|---|---|
| 1+ | $5.080 |
| 10+ | $4.840 |
| 25+ | $4.740 |
| 50+ | $4.660 |
| 100+ | $4.580 |
| 250+ | $4.500 |
| 500+ | $4.460 |
Información del producto
Resumen del producto
CY7C1021D-10VXIT is a high-performance CMOS static RAM organized as 65,536 words by 16 bits. This device has an automatic power-down feature that significantly reduces power consumption when deselected. The input and output pins (I/O0 through I/O15) are placed in a high-impedance state when the device is deselected (active-low CE HIGH), outputs are disabled (active-low OE HIGH), active-low BHE and active-low BLE are disabled (active-low BHE, active-low BLE HIGH), or during a write operation (active-low CE LOW and active-low WE LOW). Write to the device by taking chip enable (active-low CE) and write enable (active-low WE) inputs LOW. Read from the device by taking chip enable (active-low CE) and output enable (active-low OE) LOW while forcing the write enable (active-low WE) HIGH. The device is suitable for interfacing with processors that have TTL I/P levels.
- Pin and function compatible with CY7C1021B
- High speed, tAA=10ns
- VCC Operating supply current is 80mA max at 100MHz, VCC=Max, IOUT=0mA, f=fMAX=1/tRC
- Automatic CE power-down current-CMOS inputs is 3mA
- Data retention at 2.0V
- Automatic power-down when deselected, independent control of upper and lower bits
- CMOS for optimum speed and power
- Vcc is 5V ±10%
- 44-pin (400-Mil) molded SOJ package
- Industrial ambient temperature range from -40°C to +85°C
Especificaciones técnicas
SRAM asíncrona
1
0
0
44Pines
0
5
Surface Mount
85
MSL 3 - 168 hours
0
0
64K x 16bit
SOJ
4.5
5.5
-
-40
-
No SVHC (21-Jan-2025)
Documentos técnicos (2)
Alternativas para el número de pieza CY7C1021D-10VXIT
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Legislación y medioambiente
RoHS
RoHS
Certificado de conformidad del producto