PCA9541APW/03,118

PCA9541APW/03,118 is a 2-to-1 I²C-bus host selector with interrupt logic and reset. One interrupt input (active-low INT-IN) collects downstream information and propagates it to the 2 upstream I²C-buses (active-low INT0 and INT1) if enabled. Active-low INT0 and INT1 are also used to let the previous bus host know that it is not in control of the bus anymore and to indicate the completion of the bus recovery/initialization sequence. If the masking option is set, this interrupt can be disabled and does not generate an interrupt. An interrupt is sent to the upstream channel when the recovery/initialization procedure is completed. The application includes high-reliability systems with dual, gatekeeper multiplexer on a long single bus, bus initialization/recovery for server devices without hardware reset, and allows hosts without arbitration logic to share resources.

• I²C-bus interface logic; compatible with SMBus standards
• Powers up with no channel selected and Either host can take control of the bus
• Active LOW interrupt input, 2 active LOW interrupt outputs, active LOW reset input
• 4 address pins allowing up to 16 devices on the I²C-bus
• Channel selection via I²C-bus, bus initialization/recovery function
• Bus traffic sensor, low ron switches, no glitch on power-up
• Supports hot insertion, low standby current, 6.0V tolerant inputs
• 0Hz to 400KHz clock frequency, latch-up testing is done to JEDEC Standard JESD78 which exceeds 100mA
• ESD protection exceeds 2000V HBM per JESD22-A114 and 1000V CDM per JESD22-C101
• TSSOP16 package, ambient temperature range from -40 to +85°C