EK1HMC7044LP10B

EK1HMC7044LP10B is an evaluation board to evaluate the HMC7044 dual loop clock jitter cleaner. The HMC7044 meets the requirements of multicarrier GSM and LTE base station designs and offers a wide range of clock management and distribution features to simplify baseband and radio card clock tree designs. The high performance dual-loop core of the HMC7044 enables the base station designer to attenuate the incoming jitter of a primary system reference clock, such as a CPRI source, with the help of the narrow-band configured first PLL loop, which disciplines an external VCXO and to generate the low phase noise, high frequency clocks with the wider-band second PLL to drive data converter sample clock inputs.