AD9543BCPZ

AD9543 is a quad input, 10-output, dual DPLL/IEEE 1588 synchronizer and jitter cleaner. It supports existing and emerging ITU standards for the delivery of frequency, phase, and time of day over service provider packet networks. The 10 clock outputs of the device are synchronized to any one of upto four input references. The digital phase-locked loops (DPLLs) reduce timing jitter associated with the external references. It is used in applications such as PTP (IEEE 1588), and SyncE jitter clean-up and synchronization, optical transport networks (OTN), SDH, and macro and small cell base stations, OTN mapping/demapping with jitter cleaning, small base station clocking, including baseband and radio stratum 2, stratum 3e, and stratum 3 holdover, jitter clean-up, and phase transient control JESD204B support for analog-to-digital converter (ADC) and digital-to-analog converter (DAC) clocking, cable infrastructures, carrier Ethernet.

• Single 1.8V power supply operation with internal regulation
• External EEPROM support for autonomous initialization
• Supports embedded (modulated) input/output clock signals, fast DPLL locking modes
• 2 differential or 4 single-ended input references
• Crosspoint mux interconnects reference inputs to PLLs
• Slew rate for sinusoidal input is 50V/µs typical
• Resonator frequency range from 25MHz to 60MHz
• Loop bandwidth is 260KHz typical
• Operating temperature range from -40°C to +85°C
• Package style is 48-lead lead frame chip scale [LFCSP]

Notes

ADI products are only authorized (and sold) for use by the customer and are not to be resold or otherwise passed on to any third party