MT48LC4M32B2B5-6A XIT:L

MT48LC4M32B2B5-6A XIT:L SDRAM is a high-speed CMOS, dynamic random-access memory containing 134,217,728 bits. It is internally configured as a quad-bank DRAM with asynchronous interface (all signals are registered on the positive edge of the clock signal, CLK). The SDRAM provides for programmable read or write burst lengths (BL) of 1, 2, 4, or 8 locations, or the full page, with a burst terminate option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. It is designed to operate in 3.3V memory systems. An auto refresh mode is provided, along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible.

• Fully synchronous; all signals registered on positive edge of system clock, PC100-compliant
• Internal pipelined operation; column address can be changed every clock cycle
• Internal banks for hiding row access/precharge, self refresh mode (not available on AT devices)
• Auto precharge, includes concurrent auto precharge and auto refresh modes
• Auto refresh, 64ms, 4096-cycle refresh (commercial, indust), 16ms, 4096-cycle refresh (automotive)
• LVTTL-compatible inputs and outputs, supports CAS latency (CL) of 1, 2, and 3
• 4 Meg x 32 (1 Meg x 32 x 4 banks) configuration
• 167MHz clock frequency
• Industrial operating temperature range from -40°C to +85°C
• 90-ball VFBGA package