74LVC2G240DC,125

74LVC2G240DC,125 is a dual inverting buffer/line driver with 3-state outputs. The 3-state outputs are controlled by the output enable inputs 1 active-low OE and 2 active-low OE. A HIGH level at pins n active-low OE causes the outputs to assume a high-impedance OFF-state. Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall times. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of the device as a translator in a mixed 3.3V and 5V environment. It is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down. It complies with JEDEC standard (JESD8-7 (1.65V to 1.95V), JESD8-5 (2.3V to 2.7V), JESD8-B/JESD36 (2.7V to 3.6V). It features ESD protection (HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000V, CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000V).

• Wide supply voltage range from 1.65V to 5.5V
• 5V tolerant input/output for interfacing with 5V logic, high noise immunity
• CMOS low power consumption, latch-up performance exceeds 250mA
• Direct interface with TTL levels, inputs accept voltages upto 5V
• Input leakage current is ±0.1μA typ at (VI= 5.5V or GND;VCC = 0V to 5.5V, Tamb = -40°C to +85°C)
• Supply current is 0.1μA typ at (VI= 5.5V or GND;IO = 0A;VCC = 1.65V to 5.5V, Tamb = -40°C to +85°C)
• Input capacitance is 2pF typical at (Tamb = -40°C to +85°C)
• Propagation delay is 4.1ns typ at (VCC = 1.65V to 1.95V, Tamb = -40°C to +85°C)
• Operating temperature range from -40°C to +125°C
• VSSOP8 package