AS4C32M16D1A-5TCN

AS4C32M16D1A-5TCN 512Mb DDR SDRAM is a high-speed CMOS double data rate synchronous DRAM containing 512Mbits. It is internally configured as a quad 8M x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CK). Data outputs occur at both rising edges of CK and active-low CK. Read and write accesses to SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a read or write command. The refresh functions, either auto or self refresh are easy to use. By having a programmable mode register and extended mode register, the system can choose most suitable modes to maximize its performance. This device is well suited for applications requiring high memory bandwidth, result in a device particularly well suited to high performance main memory and graphics applications.

• Fast clock rate: 200MHz, differential clock CK and active-low CK
• Bi-directional DQS, DLL enable/disable by EMRS, SSTL-2 I/O interface
• Fully synchronous operation, internal pipeline architecture
• Four internal banks, 8M x 16-bit for each bank, precharge and active power down
• Programmable mode and extended mode registers, CAS latency: 2, 2.5, 3
• Burst length: 2, 4, 8, burst type: sequential and interleaved
• Individual byte write mask control, 8192 refresh cycles / 64ms
• DM write latency = 0, auto refresh and self refresh
• Power supplies: VDD and VDDQ = 2.5V ± 0.2V, 400Mbps/pin data rate
• 66 pin TSOP II package, commercial temperature range from 0 to 70°C