MC7447AHX1167NB

The MPC7447A series high-performance low-power RISC Microprocessor implements the full PowerPC 32-bit architecture and is targeted at networking applications. Key architectural features include 512kB of on-chip L2 cache, a 64-bit bus interface and a full 128-bit implementation of our AltiVec™ technology. Designed as pin-compatible replacements for MPC7447 products, this new processor has been shown to reach speeds of 1.5GHz. MPC7447A processor benefit from our silicon-on-insulator (SOI) process technology, engineered to help deliver significant power savings without sacrificing speed. Low-power versions of the MPC7447A are available. The MPC7447A offers eight instruction BAT and data BAT registers to help support lightweight embedded operating systems, enabling more large tables of data. The processors also provide cache locking to the L1 caches so that key performance algorithms and code can be locked in the L1 cache.

• Up to four instructions can be fetched from the instruction cache at a time
• Up to 12 instructions can be in the instruction queue (IQ)
• Up to 16 instructions can be at some stage of execution simultaneously
• Single-cycle execution for most instructions
• One instruction per clock cycle throughput for most instructions
• Seven-stage pipeline control
• Eleven independent execution units and three register files
• Branch processing unit (BPU) features static and dynamic branch prediction
• Four integer units (IUs) that share 32 GPRs for integer operands
• Five-stage FPU and a 32-entry FPR file - Supports non-IEEE mode for time-critical operations
• Four vector units and 32-entry vector register file (VRs)
• Three-stage load/store unit (LSU) - Supports integer and vector instruction load/store traffic
• 16 GPR, 16 FPR and 16 VR rename buffers
• Dispatch unit - Decode/dispatch stage fully decodes each instruction
• Completion unit
• 32kB, eight-way set-associative instruction and data caches
• Pseudo least-recently-used (PLRU) replacement algorithm
• 32-byte (eight-word) L1 cache block
• On-chip, 512kB, eight-way set-associative unified instruction and data cache
• Fully pipelined to provide 32 bytes per clock cycle to the L1 caches
• A total 9-cycle load latency for an L1 data cache miss that hits in L2
• Separate memory management units (MMUs) for instructions and data
• Efficient data flow
• Power and thermal management
• Reliability and serviceability